Design Verification Engineer
Hands-on industry experience at Synopsys, specializing in UVM-based verification of MIPI M-PHY IP. Strong expertise in SystemVerilog, UVM, SystemVerilog Assertions (SVA), constrained-random verification, and coverage-driven architectures. Achieved 100% functional coverage in a production-grade verification environment.
Capabilities
Technical Arsenal
🛡️ Verification & Methodology
🧩 UVM Architecture
⚡ RTL Design & Protocols
🛠️ Tools & Programming
Career
Professional Experience
Technical Engineering Intern – M-PHY Verification
Synopsys, Hyderabad, India
- ▹ Contributed to MIPI M-PHY IP verification by validating high-speed interface functionality against protocol specifications in a production-grade UVM environment.
- ▹ Developed and maintained 20+ SystemVerilog Assertions (SVA) targeting corner cases, boundary conditions, and protocol behavior to improve verification completeness and bug detection.
- ▹ Achieved 100% functional coverage for the verification scope through coverage-driven and constrained-random verification techniques.
- ▹ Performed simulation, debugging, and waveform analysis using Synopsys VCS and Verdi to identify and resolve RTL and verification failures.
- ▹ Worked across the complete UVM testbench flow, including driver, monitor, sequencer, sequence, agent, scoreboard, and coverage collector components.
Design & Verification Trainee
FutureWiz, Noida, India
- ▹ Developed strong foundations in Digital Design, Verilog, SystemVerilog, and UVM through structured industry-oriented training.
- ▹ Contributed to RTL design and verification projects using simulation-driven debugging and industry-standard verification methodologies.
- ▹ Developed SystemVerilog testbenches for digital designs and performed functional and code coverage analysis.
- ▹ Strengthened expertise in RTL simulation, waveform debugging, constrained-random testing, and verification workflows.
Portfolio
Key Projects
APB Slave Interface – RTL Design & UVM Verification
- Designed and verified an APB Slave interface in Verilog according to the AMBA APB protocol specification.
- Developed a constrained-random SystemVerilog testbench to verify protocol functionality, corner cases, and functional behavior.
- Implemented a complete UVM verification environment including agent, driver, monitor, sequencer, scoreboard, and sequence library.
8-Bit ALU – RTL Design & UVM Verification
- Designed a synthesizable 8-bit ALU in Verilog supporting arithmetic, logical, shift, and comparison operations using opcode-based control logic.
- Developed a self-checking SystemVerilog and UVM testbench to verify all supported operations and corner cases.
- Performed simulation and waveform analysis to debug functional failures and validate RTL behavior.
IoT-Based Smart Parking System
An intelligent transportation system (ITS) utilizing sensors, cloud databases, and software to optimize parking efficiency and reduce congestion.
- Features: Real-time parking availability detection, dynamic guidance systems, and mobile app integration for monitoring.
- Future Scope: Contactless payments, surveillance monitoring, and advanced pre-booking/reservation systems.
Milestones
Achievements & Certifications
University Gold Medalist
IPS Academy • 2024
Awarded the Gold Medal for academic excellence in B.Tech Electronics and Communication Engineering (GPA: 9.33).
1st Prize - Inter College Project
PIEMR Indore
Won 1st prize, a Gold Medal, and a ₹5,000 cash cheque for outstanding project presentation and execution.
Advanced Design Verification Certification
Issued by FutureWiz • March 2025
Comprehensive mastery of Digital Design, Verilog, SystemVerilog, and UVM methodologies.
Academics
Education
B.Tech – Electronics and Communication Engineering
IPS Academy Institute of Engineering and Science, Indore, India
12th Grade (Higher Secondary)
Sir Subhash Chandra Bose HS School, Satwas
10th Grade (High School)
Diamond HS School, Satwas
Let's Connect
Have an exciting opportunity, a project idea, or just want to chat about Design Verification? I'd love to hear from you.
akashbagwan.vlsi@gmail.com